15.1 Processors, Parallel Processing, and Virtual Machines

RISC and CISC processor

CISC: hardware used: the hardware should be chosen to suit the high-level language development
RISC: software/instruction sets to be used: this philosophy is driven by ever faster execution times.

Comparison

CISC Features	RISC Features
Many instruction formats are possible	Uses fewer instruction formats/sets
There are more addressing modes	Uses fewer addressing modes
Makes use of multi-cycle instructions	Makes use of single-cycle instructions
Instructions can be of a variable length	Instructions are of a fixed length
Longer execution time for instructions	Faster execution time for instructions
Decoding of instructions is more complex	Makes use of general multi-purpose registers
It is more difficult to make pipelining work	Easier to make pipelining function correctly
The design emphasis is on the hardware	The design emphasis is on the software
Uses the memory unit to allow complex instructions to be carried out	Processor chips require fewer transistors
Microprogrmmable CU

CISC(Complex Instruction Set Computer)

-Use more internal formats than RISC.
-Single complex instruction ---> number of sun-instruction

RISC(Reduced Instruction Set Computer)

-Fewer built-in instruction sets than CISC
-Assembly code instruction ---> simpler single-cycle instruction

Pipelining

[!quote]
It is a method that allows several instructions to proceed simultaneously without waiting for previous instructions to be completed.

Pipelining Process

Instructions are broken down into 5 stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Instruction Execute (IE), and Write Back (WB).

Each stage is completed in a single clock cycle.

No two instructions can execute the same stage simultaneously.

As the first instruction moves to its next stage, the second instruction starts, followed by the third in the next cycle, and so on, creating an overlap of instruction processing.

Stage of execution

![[Pasted image 20240924153629.png]]

Interrupt

When an interrupt occurs in a pipelined processor, most instructions in the pipeline are discarded, except the last one in the write-back stage. The interrupt is handled, then the processor resumes with the next instruction. Alternatively, all pipeline stages can be saved in registers for a full state restoration. This allows the processor to return to its previous state after handling the interrupt.

15.1.2 Parallel Processing

SISD(Single Instruction Single Data)

[!quote]
It uses a single processor that can handle a single instruction and also uses one data source at a time. Each task proceeds in sequential order

![[Pasted image 20240924155011.png]]

SIMD(Single Instruction Multiple Data)

[!quote]
Uses many processors. Each processor executes the same instruction but uses different data inputs – they are all doing the same calculations but on different data simultaneously.

![[Pasted image 20240924160713.png]]

Video Encoding
AI
Scientific Simulation

MISD(Multiple Instruction Single Data)

[!quote]
Uses several processors. Each processor uses different instructions but uses the same shared data source.

![[Pasted image 20240924160730.png]]

Space Shuttle
DSP

MIMD(Multiple Instruction Multiple Data)

[!quote]
uses multiple processors. Each one can take its instructions independently, and each processor can use data from a separate data source (the data source may be a single memory unit that has been suitably partitioned).

![[Pasted image 20240924160741.png]]

Parallel Computer System

[!quote]
A number of computers networked together to form a Cluster.

A massive parallel computer is

A large number of processors or separate computers are connected together.

These systems perform coordinated computations simultaneously (collaborative processing).

They rely on a network infrastructure for connectivity.

Communication between processors occurs through message interfaces, by sending and receiving messages.

![[Pasted image 20240924160005.png]]

Virtual Machine

[!Def]
A virtual machine is a software-based emulation of a physical computer that operates and runs applications like a separate and independent system.

![[CleanShot 2024-10-21 at 06.30.22@2x 1.png]]

Advantage	Disadvantage
More than one OS can be run on a computer system.	Time and effort required for implementation
	Implementation will not offer same level of performance that would be obtained on a normal system.

15.2 BOOLEAN ALGEBRA AND LOGIC CIRCUIT

Half Adder And Full Adder

Half Adder

Input		Output
A	B	Sum	Carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

S: XOR gate, C: AND gate
Universal gate: NAND, NOR (Create any circuit)

Full Adder

Input			Output
A	B	Carry (in)	S	Carry (out)
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Sequential Circuit

[!example] Role
The role of flip flop in a computer is: It is a circuit with two states used for data storage memory to store 1 bit of data.

Differences between JK and SR

SR Flip-Flop: When both S (Set) and R (Reset) inputs are 1 simultaneously, it results in an undefined/invalid/indeterminate state. This is because both outputs (Q and Q’) could potentially be 0, which contradicts their usual complementary nature.

JK Flip-Flop: It overcomes the issue of the undefined state in the SR flip-flop by toggling the output when both J and K are 1. This makes the JK flip-flop stable, as it doesn’t enter an invalid state and can handle all input combinations.

The JK flip-flop is controlled by a clock pulse, meaning that changes to the output only occur on the edge (rising or falling) of the clock signal, allowing for more precise control.

SR (Set reset) flip-flop

![[CleanShot 2024-10-21 at 06.03.52@2x.png]]
![[CleanShot 2024-10-21 at 06.00.14@2x.png]]

1, 1 as INPUT is undefined state

JK flip-flop

![[CleanShot 2024-10-21 at 06.04.14@2x.png]]
Clock can be used for synchronizing input.

![[CleanShot 2024-10-21 at 06.09.53@2x.png]]

Boolean Algebra

$\overline{A}$ is NOT A, $A.B$ is A AND B, $A + B$ is A OR B, $A \oplus B$ is XOR

Law	AND form	OR form
Identity	1. A=A	0+A=A
Null	0. A=0	1+A=1
Idempotent	A.A=A	A+A=A
Inverse	A.(NOT A)=0	A + (NOT A)=1
Commutative	A.B=B.A	A+B=B+A
Associative	(A.B). C=A.(B.C)	(A+B)+C=A+(B+C)
Distributive	A+B.C=(A+B). (A+C)	A.(B+C)=A.B+A.C
Absorption	A.(A+B)=A	A+A.B=A
De Morgan's	$\overline{(A.B)}=\overline{A}+\overline{B}$	$\overline{(A+B)}=\overline{A}.\overline{B}$